Hardware & embedded systems engineer
6+ years across RTL design, SoC-to-FPGA prototyping, post-silicon bring-up, embedded Linux, and edge ML. My RTL has gone into fabricated respin silicon; I then owned the bring-up that proved that silicon worked, and wrote the drivers and features that ran on top. The connective tissue is cross-layer debugging — problems that could live in the RTL, the constraints, the firmware, the power rail, or the kernel config.
RTL → FPGA prototyping → post-silicon bring-up → embedded Linux → drivers → edge ML
Camera ASIC (UX720V6 / Aleta S3): designed an image-composition RTL module that went into the respin silicon, then solo-owned post-silicon bring-up — test planning, validation-board revision, MIPI/DDR tuning tools, and a register-level control driver verified to images landing in DDR. Also owned an embedded Linux board bring-up on a partner product line, wrote an IMU driver with an end-to-end EIS feature, and enabled an edge-AI pipeline on RK3588.
Thesis: a 32-channel pressure-sensing system for non-contact heart-rate and respiration monitoring — hardware through embedded acquisition, ML pipeline, and INT8 edge deployment on ESP32-S3, validated with leave-one-subject-out cross-validation across 33 subjects. Earlier research: multi-modal EEG/EMG/insole sensing, where I resolved an ESP32 throughput bottleneck with a dual-bridge data path.
SoC-to-FPGA prototyping for the Dimensity 700 5G smartphone SoC on Synopsys HAPS-80/100: adapted SoC RTL partitions for the FPGA target across CPU, memory, and multimedia subsystems, handled clock/reset and timing constraints, and debugged mismatches between firmware expectations and hardware behavior. Built Perl automation that kept RTL register maps in sync with SoC CSVs — saving 1–2 weeks of cross-team debugging per project cycle.
Block-level RTL for the Aleta S2C 360° camera platform on Xilinx FPGAs: ISP blocks (RGB binning, WDR/HDR), DMA against an internal DDR controller, CDC handling, DDR3 auto-refresh for low-power transitions, five-lens synchronization — and an H.264 pipeline extension from 240×180 to 4K.
Co-authored undergraduate research on a turbidity-meter voltage-to-frequency converter chip, published in the IEEE Sensors Journal.
Proprietary details are abstracted; scope and ownership are stated as they actually were.
Respin silicon for the UX720V6 (Aleta S3) camera ASIC came back from the fab — hundreds of engineering units that had never been powered on. I owned the whole chain: test planning, revising the validation board, a voltage-aware MIPI delay-scan utility (Python) to find stable operating points, and a DDR sweep utility (C) integrated into the boot and mode-switching sequence to find per-unit optimal timing dynamically. Delivered a register-level control driver on top of the ASIC's hardware control block.
After the first UX720V6 tape-out failed, the company respun the mask. I designed and added an image-composition RTL module into the respin — the re-fabricated chips came back, were brought up, and ran. Not "taped out": my RTL is in working physical silicon.
At MediaTek, adapted SoC RTL partitions to FPGA targets through platform generations — early CPU/SRAM/MMU porting to full multimedia integration. Down-clocked clock domains, partitioned critical modules, managed the CDC/RDC risks the adaptation itself introduces, and cleaned constraint sets so the timing tools worked real paths instead of false ones (ProtoCompiler, SpyGlass, Vivado).
On a partner product line, integrated our camera ASIC onto an Anyka SoC — from the vendor BSP up through SPI-based ASIC control and the MIPI data path back to the CPU, to the first captured image. Vendor BSP as the base; the integration and bring-up were mine.
Wrote the IMU driver and owned the EIS feature end-to-end: IMU raw data through the stabilization algorithm to output coordinates, mapped onto the platform's existing PTZ coordinate system, delivered as a working feature. Separately enabled an edge-AI image-recognition pipeline on RK3588 and handed it off to the Linux team.
Built a 32-channel pressure-sensing system end-to-end for non-contact heart-rate and respiration monitoring: hardware, embedded acquisition, CNN/Transformer models, and INT8 ONNX quantization deployed on ESP32-S3. Validated with leave-one-subject-out cross-validation across 33 subjects; a Wilcoxon signed-rank test confirmed quantization preserved accuracy. Firmware, ML code, and data are open-sourced.
Three bugs that didn't live where they seemed to — told the way they happened.
Publication — co-author, turbidity-meter voltage-to-frequency converter chip, IEEE Sensors Journal.
Based in Ottawa, Canada — open to FPGA, ASIC validation / bring-up, embedded systems, and system-integration roles. Email is the reliable channel: jay@chiehnengwu.dev, or find me on GitHub.